What is the bit width of an SIMD register with the suffix of 'D' when determining subword parallelism? {Ans: 64-bit in a 128 bit wide register}What is the approximate range of an unsigned 64 bit integer? {Ans: 0 to 18,446,744,073,709,551,615}Which performance benefit do 128-bit wide registers in SSE2 streaming SIMD extensions enable? {Ans: Parallel arithmetic computations}What is superscalar as it relates to parallelization? {Ans: A technique that enables the processor to execute more than one instruction per clock cycle by selecting them during execution}What is the address of the next instruction that should execute after the branch if the register X1 is equal to 0? 28 SUB X12, X4, X8 32 CBZ X1, X5, 5 36 AND X13, X4, X7 40 ORR X14, X4, X8 44 ADD X14, X6, X4 48 SUB X15, X8, X9 52 LDUR X4, [X7,#50] {Ans: 52}Registers X1, X2, X3 have corresponding data stored in each location: X1: A X2: B X3: C Which set of ARM instructions will accomplish A=B+C? {Ans: ADD X1, X2, X3}